A long-in-development feature for AMD EPYC Zen 5 server platforms now merged for the Linux 7.0 kernel is ACPI PRMT-based address translation for the Compute Express Link (CXL) subsystem.
After going through ten rounds of code review the past number of months, this AMD Zen 5 platform feature is now upstream in the mainline Linux kernel. It’s explained in one of the kernel patches as:
“Zen5 systems may be configured to use ‘Normalized addresses’. Then, host physical addresses (HPA) are different from their system physical addresses (SPA). The endpoint has its own physical address space and an incoming HPA is already converted to the device’s physical address (DPA). Thus it has interleaving disabled and CXL endpoints are programmed passthrough (DPA == HPA).
Host Physical Addresses (HPAs) need to be translated from the endpoint to its CXL host bridge, esp. to identify the endpoint’s root decoder and region’s address range. ACPI Platform Runtime Mechanism (PRM) provides a handler to translate the DPA to its SPA.
…
With Normalized Addressing this PRM handler must be used to translate an HPA of an endpoint to its SPA.Do the following to implement AMD Zen5 address translation:
Introduce a new file core/atl.c to handle ACPI PRM specific address translation code. Naming is loosely related to the kernel’s AMD Address Translation Library (CONFIG_AMD_ATL) but implementation does not depend on it, nor it is vendor specific. Use Kbuild and Kconfig options respectively to enable the code depending on architecture and platform options.
AMD Zen5 systems support the ACPI PRM CXL Address Translation firmware call (see ACPI v6.5 Porting Guide, Address Translation – CXL DPA to System Physical Address). Firmware enables the PRM handler if the platform has address translation implemented.”
There is also a separate documentation patch that itself was through five rounds of review. This documentation covers ACPI PRM CXL Address Translation in more detail.
This ACPI Platform Runtime Mechanism (PRM) / Platform Runtime Mechanism Table (PRMT) debuted with AMD EPYC 9005 series but will presumably continue to be built upon in next-gen EPYC Zen 6 platforms too. So while it’s late in arriving in the mainline kernel, at least it’s here now and ready for the future.
The CXL merge for Linux 7.0 also brought CXL port error protocol handling and reporting additions and various other code clean-ups and fixes.
