Upstreamed to LLVM/Clang overnight is now targeting support for the SiFive P550 RISC-V core with the “-mcpu=sifive-p550” option.
The P550 is one of SiFive’s performance cores that features a thirteen-stage, triple-issue, out-of-order pipeline. SiFive talks up the P550 as offering 30% higher performance in less than half the area of a similar Arm Cortex-A75 core. The P550 can be found in up to a four-core design.
With this merge to LLVM Git ahead of the LLVM/Clang 20 release in the coming months, the SiFive Performance P550 can now be targeted using the -mcpu=sifive-p550 option. Though no specialized scheduler model yet for the P550 but the patch says a P550 scheduler model will be added later in a separate patch. At least this gets the P550 support started for enabling RISC-V plus the various RISC-V extensions supported by this performance core like Zba, Zbb, and Zifencei.
Making this Clang support more notable is the SiFive P550 is what’s found in the HiFive Premier P550 RISC-V developer board. Though sadly still no word from SiFive on any review sample and thus no ability yet to run any independent performance benchmarks on this P550 performance core.
