CXL Address Translation Support For AMD Zen 5 Sees Linux Patches

A set of Linux kernel patches posted by AMD engineers last week are working on enhancing the CXL address translation support between the HPA decoder and system physical memory addresses. These patches get that CXL address translation support working for the recently launched AMD EPYC 9005 “Turin” Zen 5 server processors.

Robert Richter of AMD sent out these patches for the Linux kernel to support address translation in the context of the Compute Express Link (CXL) subsystem and enabling it for AMD Zen 5 platforms. This is needed since the current CXL Linux driver doesn’t implement address translation and makes the assumption of the host physical address (HPA) and system physical address (SPA) being the same.

The AMD patch series further explains the situation:

“Systems with different HPA and SPA addresses need address translation. If this is the case, the hardware addresses esp. used in the HDM decoder configurations are different to the system’s or parent port address ranges. E.g. AMD Zen5 systems may be configured to use ‘Normalized addresses’. Then, CXL endpoints have their own physical address base which is not the same as the SPA used by the CXL host bridge. Thus, addresses need to be translated from the endpoint’s to its CXL host bridge’s address range.

To enable address translation, the endpoint’s HPA range must be translated to each of the parent port’s address ranges up to the root decoder. This is implemented by traversing the decoder and port hierarchy from the endpoint up to the root port and applying platform specific translation functions to determine the next HPA range of the parent port where needed.”

The AMD Zen 5 support relies upon the ACPI Platform Runtime Mechanism (PRM) for the address translation.

See this Linux kernel patch series now under review for those interested in CXL on AMD Zen 5 servers.