Intel updated their AVX10 whitepaper and associated open-source compiler patches around this next Advanced Vector Extensions standard… While AVX10 had intended to allow either 256-bit or 512-bit modes depending upon processor capabilities, Intel has dropped the 256-bit-only approach and going for 512-bit everywhere. Thus it would seem to indicate that Intel E cores of the future will properly support AVX 512-bit operation!
It looks like AMD’s widespread support for AVX-512 since Zen 4 and the rather confusing AVX10 implementations previously pursued by Intel are now over. With updated GCC compiler patches posted today, that 256-bit mess proposed for future AVX10 versions is being removed.
Intel today posted a new AVX10 whitepaper where they drop the 256-bit references:
“Removed references to 256-bit maximum vector register size, enumeration of vector-length support, and 256-bit instructions supporting embedded rounding.”
The whitepaper previously noted “optional 512-bit FP/int” support up to now along with other 256-bit references:
But with today’s v3.0 revision to the AVX10 whitepaper, that “optional 512-bit” reference on AVX10.2 is now clearly removed:
It also indicates that this AVX10.2 support will be found on both P and E cores.
Within GCC patches posted today it’s also spelled out clearly:
“In this new whitepaper, all the platforms will support 512 bit vector width (previously, E-core is up to 256 bit, leading to hybrid clients and Atom Server 256 bit only). Also, 256 bit rounding is not that useful because we currently have rounding feature directly on E-core now and no need to use 256-bit rounding as somehow a workaround. HW will remove that support.
Thus, there is no need to add avx10.x-256/512 into compiler options. A simple avx10.x supporting all vector length is all we need. The change also makes -mno-evex512 not that useful. It is introduced with avx10.1-256 for compiling 256 bit only binary on legacy platforms to have a partial trial for avx10.x-256. What we also need to do is to remove 256 bit rounding.”
This is a rather late shift for Intel. Since AVX10 was announced in 2023 there was the possibility of this 256-bit max vector width. But now it seems AVX10 hardware will all have 512-bit vector width support. This is great news for future E core processors both on the desktop and then the dense Xeon E-core server platforms. With this being a late change, Intel compiler engineers are working on these last minute alterations to the GNU Compiler Collection ahead of the upcoming GCC 15.1 stable release due out in the coming weeks… Really a last minute squeeze to get these AVX10 modifications in place for GCC 15. GCC 15 is what provides initial AVX10.2 support and when merged last year had added both the 256-bit and 512-bit modes.
Great seeing this logical change happen but unfortunate this decision was made two years after announcing AVX10. Going for full 512-bit everywhere will hopefully clear up the x86_64 micro-architecture feature level handling moving forward too for not having to now deal with this 256-bit vs. 512-bit limitation. This will also allow future Intel Xeon E-core processors to better compete with AMD’s dense EPYC core designs that since the introduction with Bergamo (Zen 4C) have supported AVX-512 everywhere.
