The GCC 15.1 compiler release is expected in the coming weeks as the first stable version of GCC 15 as this annual GNU Compiler Collection release. As we approach the finish line, some last minute changes were merged for the AMD Zen 5 “znver5” CPU target.
There are some last minute adjustments happening to the GCC 15 compiler around its AMD Zen 5 optimizations for the EPYC 9005 and Ryzen 9000 series / Ryzen AI 300 series processors.
First up, the znver5 issue rate was lowered from 6 to 4. The commit explains:
“This patch sets issue rate of znver5 to 4. With current model, unless a reservation is missing, we will never issue more than 4 instructions per cycle since that is the limit of decoders and the model does not take into acount the fact that typically code is run from op cache.”
Another patch merged to GCC Git today adjusts the ADDSS/SD SUBSS/SD instructions cost from 2 to 3. The rationale there is:
“Set ADDSS cost to 3 for znver5
Znver5 has latency of addss 2 in typical case while all earlier versions has latency 3. Unfortunately addss cost is used to cost many other SSE instructions than just addss and setting the cost to 2 makes us to vectorize 4 64bit stores into one 256bit store which in turn regresses imagemagick.
This patch sets the cost back to 3. Next stage1 we can untie addss from the other operations and set it correctly.”
Those two patches were authored by SUSE compiler engineer Jan Hubicka.
While AMD has a growing compiler team and contributes a lot to LLVM and their LLVM-downstream AOCC, when it comes to GCC AMD has traditionally relied on their partners at SUSE for carrying out most of the AMD Zen target upstreaming and various compiler optimization tuning for their processors. We’ll see if any other late Znver5 changes make it into the compiler ahead of the upcoming GCC 15.1 stable release.
Fresh GCC 15 AMD and Intel compiler performance benchmarks upon the GCC 15.1 release.
