Queued within the development tree for the RISC-V processor code for the Linux kernel is supporting several new vendor-specific ISA extensions for SiFive RISC-V CPU cores.
Making it this past week into riscv/linux.git’s “for-next” branch ahead of Linux 6.16 is this merge for enabling some new SiFive vendor extensions for RISC-V. Four SiFive vendor extensions are set to be introduced with this code for Linux 6.16: xsfvqmaccdod, xsfvqmaccqoq, xsfvfnrclipxfqf, and xsfvfwmaccqqq.
xsfvqmaccdod is for the SiFive Int8 Matrix Multiplication Extensions.
xsfvqmaccqoq is for the SiFive Int8 Matrix Multiplication Extensions.
xsfvfnrclipxfqf is for SiFive FP32-to-int8 Ranged Clip Instructions.
xsfvfwmaccqqq is SiFive’s Matrix Multiply Accumulate Instruction.
These new SiFive vendor-specific ISA extensions will be found on some of their upcoming RISC-V core designs. Look for this kernel-side support to be found in Linux 6.16. Compiler work around making use of these SiFive extensions and more continue for both the GNU/GCC and LLVM toolchains.
