One of the interesting new additions with the upcoming Intel Xe3 integrated and discrete graphics is the Variable Register Thread “VRT” feature. Making use of Variable Register Thread can reduce register splitting, reduce bandwidth consumption, and improve overall performance. More background information on Intel VRT can be found in that aforelinked Phoronix article. But now the ability is coming to optionally disable VRT.
Variable Register Thread sounds quite enticing and the limited performance numbers tossed around in the original merge request are very promising. Coming as somewhat of a surprise though is this past week the support was merged to be able to disable Variable Register Thread by the Intel Iris Gallium3D and ANV Vulkan drivers within Mesa.
This merge request was merged into the upcoming Mesa 25.2:
“Add support for disabling the VRT (Variable Register Thread) feature. The strategy here is to force the old BRW_MAX_GRF limit for the register allocator (locks the upper limit) and make sure ptl_register_blocks() always return that amount of blocks (locks the lower limit).”
Disabling of the Variable Register Thread when running on the upcoming Intel Xe3 graphics can be done via the INTEL_DEBUG=no-vrt environment variable prior to starting OpenGL/Vulkan software.
The INTEL_DEBUG=no-vrt option will be handy for being able to easily quantify the performance impact of Variable Register Thread though leaves me wondering why they only added this option months after plumbing Xe3 VRT support into Mesa to begin with or if there is any other motivation/need at this point for adding this VRT toggle. Hopefully the Intel VRT support is in good shape for Xe3 as sounded quite exciting and to have a measurable performance benefit.
Xe3 graphics are making their debut in integrated form with the upcoming Panther Lake SoCs and then later on will be found in discrete form with the Celestial graphics cards.
