Intel Xeon 6+ was the other main protagonist of the event that Intel recently held in Arizona, where we also saw the Intel Panther Lake generation, and which we had the opportunity to attend. This new generation of Xeon processors, also known by the code name Clearwater Forest, represents an important step forward due to its Disaggregated and agnostic modular design.
A total of three different nodes coexist in an Intel Xeon 6+ processor: Intel 18A, Intel 3 e Intel 7and uses a Modular stacking design of compute blocks, activation blocks and I/O blocks.
Intel 18A node seen at wafer level.
For interconnection and communication, Intel has used two of its star technologies, EMiB, which operates in 2.5D, and Foveros Direct 3Dwhich as its name suggests opens the doors to 3D packaging.
Internal design of the Intel Xeon 6+
Internally, an Intel Xeon 6+ has 288 E cores based on the Darkmont architecture. These are divided into a total of 12 compute blocks fabricated on Intel 18A nodeone of the most advanced that exists.
This node uses RibbonFET transistorswhich reduce the risk of electrical leakage, and use the PowerVia power system, which supplies power through the back of the transistors.
The computing blocks sit on three base activation blocks, manufactured on Intel node 3and on the sides we have of I/O blockswhich contain the PCIe and USB subsystems. These are manufactured in the Intel node 7. At the base we find 12 EMIB 2.5D blocks, which play a fundamental role in the interconnection of all these elements.
To make all that stacking of computing blocks work Intel has turned to Foveros Direct 3D, an advanced packaging technology that allows stacking blocks (also known as chiplets) of silicon vertically starting from a silicon base block that serves as a connecting link.
The interconnection of these blocks is carried out through silicon vias (TSV) and hybrid copper-to-copper junctions (HBI), which helps minimize the distance between blocks, thereby improving latency and performance.
This is very important, because The proximity between chiplets can make a big difference in terms of latency and performance. For example, a design where the chiplets are very far apart would have a very high latency, and it would be necessary to compensate for this through the communication system between those and the rest of the blocks.
A look at the Intel Xeon 6+ blocks
Each I/O block has 8 accelerators compatible with Intel QuickAssit, Intel Dynamic LoadBalancer, Intel Data Streaming and Intel In-Memory Analytics. They also have:
- 48 PCIe Gen5 lanes.
- 32 CXL 2.0 lines.
- Up to 96 UPI 2.0 lines.
In each base activation block we have four channels of DDR5 memory, 192 MB of shared L3 cache, and 48 MB of L3 cache for each compute block. The computing blocks sit on these, following a ratio of three to one.
The computing block is made up of 6 modules, four cores per module and has a total of 24 Darkmont cores per block. In each module we have 4 MB of L2 cache, so in total one block adds 24 MB of L2 cache.
Darkmont architecture: a look at what’s new
The jump to the Intel 18A node is, without a doubt, one of the most important innovations that Intel has introduced in the new Xeon 6+, but we must not forget the other big star, Darkmont architecture.
This architecture is perfectly tailored to take full advantage of the new Intel 18A nodeand brings important changes that have allowed a great improvement in performance per watt consumed. These are the most relevant:
- 64 KB instruction cache on the front-end.
- Improvements and greater precision in the jump predictor.
- 50% more bandwidth (3 X 32 bits).
- Out-of-order execution engine improvements.
- Improvements in the execution engine, both at the integer and vectorization level.
- Improvements to the memory subsystem, with advanced preloading and L1 ECC cache (error correction).
Compared to Crestmont, the architecture used in Sierra Forest (Intel Xeon 6), is expected a double-digit CPI improvement at Darkmont, according to Intel.
Intel Xeon 6+ Performance and Keys
Compared to the Intel Xeon 6 (Sierra Forest), Intel has confirmed to us that it expects a performance improvement of up to 90%an efficiency improvement of up to 23% and a significant reduction in total cost of ownership, with a consolidation of servers from 8 to 1.
Below we leave you a summary with the key specifications of these new processors:
- Up to 288 E cores (Darkmont).
- Compatible with one and two socket configurations.
- TDP between 300 and 500 watts for each CPU.
- L2 cache up to 288 MB.
- L3 cache up to 576 MB.
- Twelve DDR5 memory channels at a maximum of 8,000 MT/s.
- Up to 6 UPI 2.0 lines.
- Up to 96 PCIe Gen5 lanes.
- Up to 64 CXL 2.0 lines.
- Soporte de Intel Software Guard Extensions e Intel Trust Domain Extensions.
- Intel Application Energy Telemetry and Intel Turbo Rate Limiter to improve energy consumption management.
- AI acceleration through Invel Advance Vector Extensions 2 (VNNI and INT8).
- Up to 16 specialized accelerators (Intel QuickAssit, Intel Dynamic LoadBalancer, Intel Data Streaming and Intel In-Memory Analytics).
These new processors will also be available at early 2026and will be aimed at tackling different workloads, including 5G networks and cloud computing.
