Back in November AMD began posting open-source Linux graphics driver patches for some next-gen graphics IP. Those IP block patches were for MMHUB, PSP, and other blocks making up modern AMD GPUs. The GFXHUB patch pointed it to being part of the GFX12 / RDNA4 family. Out today are new patches for enabling the SMU15 IP and an interesting takeaway there is some apparent NPU integration for future Radeon graphics.
Posted to the public mailing lists today were enablement patches in the AMDGPU kernel graphics driver for SMU 15.0, a new version of their System Management Unit (SMU) IP for Radeon hardware. The copyright on the patches are for 2025 and presumably tie in to the other IP blocks with patches from November, since there were no SMU patches posted then, but presumably took longer to clear legal review or other factors.
While patches for the AMD graphics SMU are typically not too interesting, when I was digging through the new code my curiosity was raised as to a common AMDGPU SMU header file they introduced a METRICS_AVERAGE_NPUCLK type…. The Radeon kernel graphics driver now referencing a neural processing unit (NPU) clock speed?
Digging further into the new SMU15 code, indeed there is now an NPU clock frequency referenced within this new code. I also went to check back in the existing AMDGPU SMU14 code and there are no similar NPU references there.
Keeping in mind these NPU clock references are for the AMDGPU kernel graphics driver.
Future AMD Radeon graphics processors also pairing an NPU onboard? It’s possible this SMU 15 IP now referencing an NPU could be for future Radeon graphics cards opting for adding an NPU too for helping with AI. Or it could be around increased integration for future Ryzen AI SoCs with NPU and integrated graphics. Though the AMDGPU SMU doesn’t take into account the CPU clock frequency or the like so it’s not clear why the AMDGPU SMU would now be taking into account the NPU clock frequency, unless it’s being shifted so the NPU would be more under the Radeon GPU scope and power envelope? In that context it would make sense for better interoperability / sharing and the like for AI workloads making use of both the AMD GPU and NPU.
In any event, seeing these SMU 15.0 patches today my main takeaway from looking at the code was this addition noting an NPU. The SMU 15.0 patches were joined by SMUIO 15.0 and THM (thermal) 15.0 IP too, now out on the public mailing list for review and incorporation into a future version of the Linux kernel.
