AMD has announced that Epyc Venice, the sixth generation of its high -performance computing processors, will be the first HPC product of the industry to be developed and manufactured Under TSCM N2 Process Node. At the same time, the company has announced the validation of the fifth generation for its production at the Arizona plant. Like Nvidia, a part of AMD chips production will move to the United States.
«TSMC has been a key partner for many years, and our close collaboration with its R&D and manufacturing equipment has allowed AMD to constantly offer leading products that exceed the limits of high performance computing»said Dr. Lisa Su, Executive Director of AMD. “Being a leading HPC client for the N2 process of TSMC and for the TSMC Plant Arizona Fab 21 are excellent examples of our close collaboration to boost innovation and offer advanced technologies that will boost the future of computing”he stressed.
Epyc Venice of 2 nm
AMD’s announcement comes after his great rival in CPUS for servers, Intel, delayed the launch of its next -generation Xeon Forest ‘processor made under its own manufacturing technology. In the delicate current situation of Intel, There are serious doubts that I can compete with the N2 of TSMCthe first Foundrie of the planet and which has the most advanced technological manufacturing processes.
The EPYC Venice of Sixth Generation of AMD will be based on microarchitecture Zen 6 of the company and will be launched at some point in 2026. Beyond AMD’s own technologies under the new architecture, its great novelty will be the premiere of its manufacturing node, with TSMC production in spectacular 2 nanometers that reach almost the limit of the silicon.
The fact that AMD already has chips to talk about highlights the long collaboration between AMD and TSMCas well as the culmination of joint efforts to make chips with one of the most advanced process technologies that TSMC has developed to date. For now, AMD has not published more details of these Epyc Venice, although the company’s press release states that silicon has been recorded and uploaded, which means that the CCD has been successfully lit and the basic functional tests and validation have passed.
The N2 of TSMC is the first process technology in the chips smelting that is based on nanolminas transistors with technology gate-all-around or gaa. The company expects this technology to offer a 24 % to 35 % reduction in energy consumption or a 15 % increase in constant voltage yield, in addition to a transistor density 1.15 times higher than that of the previous generation N3 (3 Nm class).
All these improvements of the type of transistors and the N2 Nanoflex design and technology co -ptimization framework are the ones that AMD intends to take advantage of for its next generation of CPUS for HPC, the EPYC Venice.
