AMD has shared details of its new generation of servers processors, Epyc Venice, in its event ‘advancing with AI’ where the star announcement has been the launch of the Instancers Instinct Mi350.
The Epyc Venice are based on the new microarchitecture Zen 6 And TSMC will manufacture them with the 2 nanometers process technology, the most advanced in the industry. They can include up 256 processing coresa substantial increase compared to EPYC processors based on current Zen 5c, which have a maximum of 192 cores.
This expanded nucleus count is intended to improve the performance of the workloads of large -scale servers and data centers applications. One of the key characteristics of these processors is their support for 128 carriles PCIe 6.0 arranged in a double channel configuration. This coincides with previous information related to the next AMD SP7 platform.
The processor’s memory subsystem admits speeds of at least 12,500 TM/s, which is very close to the maximum speed of the second generation MRDIMM MRDIMM Speaker. With 16 memory channels operating at 64 bits each, Venice can offer a spectacular memory bandwidth of up to 1.6 Terabytes per second.
EPYC VENICE PERFORMANCE
AMD projects a yield increase up to 70% compared to the previous generation. In nucleus performance, this means that each Zen 6C nucleus will offer approximately 27.5% improvement against current Zen 5C. The series will also double the bandwidth for communication between the CPU and the GPU, which can further accelerate the workloads that take advantage of integrated or discrete GPUs in server systems.
These improvements indicate that AMD is focused on addressing the growing demands of AI, automatic learning and other high performance computer tasks in data centers. Epyc Venice is expected to be available in 2026like the next generation of the manufacturer’s AI accelerators, the MI400 series that is also in development.
