In addition to talking up the openSFI firmware collaboration between AMD and Intel at the OCP Global Summit 2025, AMD engineer Raj Kapoor provided a status update on the company’s much anticipated openSIL effort for working to ultimately replace AGESA with a new open-source CPU silicon initialization codebase.
AMD openSIL updates at Open Compute Project events have sort of become an annual tradition since openSIL was announced back in early 2023 at the OCP Prague event. At the recent OCP Global Summit in San Jose was the latest update on openSIL and those slides / video recordings are now available.
AMD continues investing in open-source firmware for greater trust and transparency. With the hyperscalers it can mean easier customization as well as faster integration and all around a growing industry interest in open-source firmware by the hyperscalers like those involved with OCP.
AMD did release the openSIL Firmware Architecture Specification “FAS” 1.0 release as part of the OCP efforts. This is a public document with all the technical firmware specifications around openSIL to aide developers.
AMD also recently published the long-awaited openSIL code for Phoenix SoCs. The AMD openSIL presentation also reaffirmed plans for 6th Gen AMD EPYC “Venice” with openSIL. They plan to open-source their Venice openSIL code around one quarter after those 6th Gen EPYC CPUs ship. They say that open-source will be in 2026, so that would mean Venice is launching in Q3 or earlier. Meanwhile the AMD Ryzen Zen 6 “Medusa” openSIL code will come in the first half of 2027.
They will be continuing with initially NDA’ed openSIL code prior to hardware launches and then open-sourcing new platform code after the fact.
Public pull requests will be permitted to openSIL for properly evaluated changes.
Raj Kapoor’s OCP Global Summit 2025 presentation on AMD openSIL is embedded below.
