Efficient Computer targets edge workloads with highly efficient Electron E1 chip launch – News

Low-power computer chip startup Efficient Computer Co. today announced the launch of its new flagship Electron E1 processor, dramatically reducing the energy requirements of general-purpose computing workloads.

The Electron E1 processor is available to developers now, alongside the company’s new effcc Compiler, which is a tool that helps to simplify how applications are integrated with the hardware.

Efficient Computer’s new chip is based on what the company says is a novel “Fabric architecture” that’s designed to enable spatial dataflow computing. It’s a fundamentally different approach to traditional computer chips, such as Intel Corp.’s x86 chips, which are based on the Von Neumann architecture, providing significant gains in terms of energy efficiency.

The company explained that Von Neumann chips waste tons of energy because they’re forever transferring data back and forth between the memory and processing cores. By eliminating this overhead, Efficient Computer says it can increase the energy efficiency of some computing workloads by up to 100 times.

That makes the Electron E1 a compelling proposition for deploying edge computing devices such as sensors, wearables and drones, which often need to rely on battery power and therefore need to be careful about conserving energy to extend their operating time.

“We’re doing something that has the capability of a CPU but is one or two orders of magnitude more efficient,” Efficient Computer co-founder and Chief Executive Brandon Lucia told IEEE Spectrum in an interview.

A Fabric dataflow architecture

With its new Fabric architecture, Efficient Computer says it’s able to lay out a software program’s instructions spatially, as opposed to processing them sequentially from the memory, as is the case with Von Neumann-based chips.

Basically, Von Neumann chips receive instructions from the memory one at a time. Those instructions tell the processor what to do with the data – for example, add it to something, reverse it or alter the format – and then the result of that operation is returned back to the memory. After that, it sends the next instruction to the processor, which performs the required operation and returns it back, ad infinitum.

The problem with the Von Neumann approach is that it’s incredibly inefficient, with instructions being pulled from the memory, processed and the results returned, several billion times per second. It eats up tons of energy, and there are overheads too, such as the need for branch prediction logic to predict what instruction will come next.

The Electron E1, on the other hand, maps out an entire sequence of instructions as a spatial pathway that the data moves through. According to Lucia, it can be thought of as an “array of tiles” linked together in a sequence. Each one is essentially a stripped-down processor core that’s able to perform a set of instructions, but without the fetching, branch prediction and other overheads.

The effcc Compiler reads the software program and assigns each instruction to a particular tile. Once the instruction is processed, the result of that becomes the input for the next tile. All of the instructions are ordered in the right sequence, enabling the program to run much more efficiently by eliminating the constant back-and-forth to the memory. If the program sequence branches, such as when it encounters an if/then/else scenario, then the spatial pattern of the tiles will also change, similar to how a railroad operator flips a switch to alter the railway tracks.

Efficient Computer says the Electron E1 is targeted at embedded and edge artificial intelligence workloads, which struggle with the limitations of existing central processing units. The chip is already being sampled by early-access customers across various industrial and aerospace verticals.

The company also has plans to launch an even more powerful version of the chip called the Photon P1, which will extend its spatial computing architecture to larger-scale edge computing workloads.

Images: Efficient Computer