Europa Keep betting on Get autonomy in the largest possible technological fields. As in the high performancefor what you are betting on developments based on RISC-V architecture with the Dare project. Abbreviation for digital autonomy with RISC-V in Europe, the project adds so far 38 actors in the technological sector for their financing and development.
Its objective is to develop capable processors, in quantity and power, to integrate into high performance computing systems so that both the continent supercomdators and other equipment considered high performance work.
The Dare project has the support of the EuroHPC initiative, and is coordinated by Barcelona Supercomputing Center (BSC-CNS). Its purpose is to develop three chip trochers that can be combined to develop complete processor packages.
The initiative has already selected those responsible for the development of each of them. The first will be a chipplet vector-mathematical accelerator, adapted for high-performance computing work loads (HPC), and the chips design company of Barcelona Openchip will lead it.
The second, in charge of the Startup of the Netherlands Axelera aiit will be a Cnext generation inference hipletwhile the third will be a general purpose chiplet, which will be in charge of the German Codasip.
The planned duration of the Dare project is six years, and for its first phase there is a budget of 240 million euros. Those responsible for DARE have also set the objective of developing the chiplets with RISC-V architecture mentioned within a maximum period of three years
Axelera AI, to which Eurohpc has granted 61.6 million euros of financing, seems to be the most advanced of all in the process of creating its chiplet. They will call it Titania, and although most of the chips that the company has developed are currently focused on the execution of AI models in the EDGE, this chipplet will be prepared to assume workloads at the server level.
«DARE is daring to start from the top of the technological complexity pole and produce European-designed processors chips for supercomputers, paving the way for Europe’s digital sovereignity,» Osman Unsal, DARE principal investigator at BNC-CNS, said in a statement.
Axelera chips, in principle, follow a formula similar to that of others, such as Google tensioning process units. The chips currently develops have four acceleration cores, each with a multiplier-accumulating matrix (MAC), a RISC-V control nucleus to make the accelerator programmable, and several digital signal processors, responsible for managing the activation functions of the neuronal network.
These Mac units, responsible for most of the AI process today, are integrated into a SRAM pool, allowing a memory process such as the current classic. Titania will have the same basic formula, but at a scale, with more process nuclei in the chiplet and multi -dead packaging system designs.
As to Codasipit already offers CPU CPU-V nuclei of 32 bit of integrated class, and 64 bit of application level. Apparently they are designed for cases of EDGE of the Network, IoT and personal computing devices of limited power. With the Dare project they will have the necessary resources To expand your product portfolio To include high performance applicationssuch as AI, the Big Data process and the supercomputing. As for the Openchip projectstill There is not much information about ChipleT Accelerator that will build.
