Intel engineers have recently been working on the notion of cache-aware scheduling / load balancing for benefiting the likes of Intel and AMD processors sporting multiple caches. Posted today was the newest iteration of these patches that are still seeking to get more feedback and testing around this potential useful addition to the Linux kernel.
Intel engineers today posted the latest spin of cache-aware scheduling patches for the Linux kernel. SOme issues were addressed from the prior code as well as mitigating a performance regression observed in the prior RFC patches.
The intent with the cache aware scheduling is to be able to aggregate tasks with likely shared resources into the same cache domain for better cache locality. Intel engineers have been testing this cache aware scheduling with Xeon “Emerald Rapids” and EPYC “Milan” processors thus far. They have found cache aware scheduling to improve the tail latency when the last level cache was under-loaded but there are still some performance issues being explored for when the last level cache is saturated.
Those interested in the prospects of cache aware scheduling for the Linux kernel can find the new patches out today on the Linux kernel mailing list.
