Merged a few days ago for the Linux 6.15 kernel were all of the performance events updates for which there are a few notable patches on the AMD and Intel side this cycle.
Within all of the kernel’s performance events code there has been some code clean-ups/simplifications ongoing in the core code and other mostly small, low-level code changes.
One item catching my attention among the AMD x86 PMU patches is adding support for OP Load Latency Filtering, which is a new feature found with the Zen 5 processors. The patch explaining this new AMD Load Latency Filtering characterizes it as:
“A new Load Latency Filtering capability is added to IBS Op pmu with latest (Zen5) uarch. It’s advertised by CPUID_Fn8000001B_EAX bit 12. When enabled, IBS hw will raise interrupts only for samples that had an IbsDcMissLat value greater than N cycles, where N is a programmable value defined as multiples of 128 (i.e., 128, 256, 512 etc.) from 128-2048 cycles. L3MissOnly is a mandatory dependency for LdLat, and like L3MissOnly, Hardware internally drops the sample and restarts if the sample does not meet the filtering condition.
Add support for LdLat filtering in IBS Op pmu. Since hardware supports threshold in multiple of 128, add a software filter on top to support latency threshold with the granularity of 1 cycle between [128-2048].
Example usage:
# perf record -a -e ibs_op/l3missonly=1,ldlat=128/ — sleep 5″
There is also some minor fixes and code cleaning to the AMD PMU code but this new Load Latency Filtering feature is the most interesting of the work this cycle.
Over on the Intel PMU side, there is a change there to mention and it’s the PEBS counters snapshotting. PEBS in the context of Intel is Performance Events Based Sampling. That patch explains the PEBS counter snapshotting as:
“The counters snapshotting is a new adaptive PEBS extension, which can capture programmable counters, fixed-function counters, and performance metrics in a PEBS record. The feature is available in the PEBS format V6.
The target counters can be configured in the new fields of MSR_PEBS_CFG. Then the PEBS HW will generate the bit mask of counters (Counters Group Header) followed by the content of all the requested counters into a PEBS record.
The current Linux perf sample read feature intends to read the counters of other member events when the leader event is overflowing. But the current read is in the NMI handler, which may has a small gap from overflow. Using the counters snapshotting feature for the sample read.
Add a new PEBS_CNTR flag to indicate a sample read group that utilizes the counters snapshotting feature. When the group is scheduled, the PEBS configure can be updated accordingly.”
See the performance events pull for the full list of feature patches in this area of perf for the Linux 6.15 merge window.
