The PCI subsystem updates were merged today for the in-development Linux 6.18 kernel. The PCI changes this cycle are mostly a random assortment of different changes to the wide assortment of PCIe drivers. Standing out is a workaround for dealing with a possible PCI Express performance issue for latest-generation Xeon 6 servers.
Today’s PCI pull request for Linux 6.18 notes of a Xeon 6 workaround for dealing with a PCIe performance issue:
“- Add a Xeon 6 quirk to disable Extended Tags and limit Max Read Request Size to 128B to avoid a performance issue (Ilpo Järvinen)”
The actual patch merged for Linux 6.18 goes on to explain the Xeon 6 PCIe performance issue in more detail:
“When bifurcated to x2, Xeon 6 Root Port performance is sensitive to the configuration of Extended Tags, Max Read Request Size (MRRS), and 10-Bit Tag Requester (note: there is currently no 10-Bit Tag support in the kernel). While those can be configured to the recommended values by FW, kernel may decide to overwrite the initial values.
Add a quirk that disallows enabling Extended Tags and setting MRRS larger than 128B for devices under Xeon 6 Root Ports if the Root Port is bifurcated to x2. Use the host bridge’s enable_device hook to overwrite MRRS if it’s set to >128B for the device to be enabled.
The earlier attempts to implement this quirk polluted PCI core code with the checks necessary to support this quirk. Using the enable_device hook keeps the quirk well-contained, away from the PCI core code.”
The prior mailing list discussion on the patches went on to note some complexities with the pre-merged kernel such as the Linux kernel’s “CONFIG_PCIE_BUS_PERFORMANCE” overwriting the BIOS defaults and actually leading to worse performance contrary to the “PERFORMANCE” option.
PCI subsystem maintainer Bjorn Helgaas also initially commented on the matter:
“This is kind of weird. It’s apparently not an erratum in the sense that something doesn’t *work*, just something for “optimized PCIe performance”?
What are we supposed to do with this? Add similar quirks for every random PCI controller? Scratching my head about what this means for the future.
What bad things happen if we *don’t* do this? Is this something we could/should rely on BIOS to configure for us?”
In any event for Linux 6.18 this Intel Xeon 6 PCIe performance “fix” or “workaround” is merged.
