Chip and silicon intellectual property technology company Rambus Inc. today announced HBM4E Memory Controller IP, a new solution that delivers breakthrough performance with advanced reliability features that allow designers to address the demanding memory bandwidth requirements.
Pitched as an industry first, the new Rambus HBM4E Controller is designed to meet the escalating memory bandwidth demands of next-generation artificial intelligence accelerators, graphics processing units and high-performance computing systems. The controller supports operation at up to 16 gigabits per second per pin to deliver as much as 4.1 terabytes per second of memory bandwidth per HBM4E device.
An HBM4E device is a high-bandwidth memory stack that uses vertically stacked DRAM dies connected through through-silicon vias to deliver extremely high memory bandwidth and low latency for AI and high-performance computing systems.
The new solution, when used in an AI accelerator configuration with eight attached HBM4E stacks, supported total memory bandwidth of more than 32 terabytes per second, a level ideal for large-scale model training, inference and data-intensive high-performance computing workloads.
High-bandwidth memory has become a foundational technology for modern AI silicon and helps to address the widening gap between compute throughput and memory access speeds. Rambus is positioning its controller IP to support the next wave of AI system-on-chip designs, where memory bandwidth and latency are critical differentiators.
The new HBM4E Controller builds on Rambus’s track record of more than 100 HBM design wins and the company’s long-standing focus on memory interface IP. The new controller incorporates advanced reliability features intended to help customers achieve first-time silicon success, a key concern as chip complexity and manufacturing costs rise.
The controller IP can be paired with third-party standards or through-silicon via PHY solutions to create a complete HBM4E memory subsystem within 2.5D or 3D packaging. The flexibility allows for integration into AI SoCs or custom base die implementations and supports a range of architectural approaches across cloud, enterprise and edge deployments.
The IP is available for licensing immediately, with early access programs open to design customers.
Images: Rambus
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