In an industry where time-to-market and verification quality directly impacts product success, Aparna Mohan has established herself as a prominent figure in the field of design verification. As a core member of the team at Cirrus Logic, Aparna Mohan spearheaded the development and implementation of a digital and mixed-signal verification framework that has become the standard across all of the company’s audio product lines.
The ambitious framework project tackled one of the semiconductor industry’s most persistent challenges: creating a standardized, reusable verification environment that could effectively test the complex intersection of digital and analog domains in modern audio chips. With her extensive background in functional verification methodologies and system-level verification, Aparna brought a unique perspective to this critical initiative.
Aparna’s methodical approach to verification architecture and implementation stands at the center of this success story. By formalizing the verification methodology, she created a system that dramatically simplified the integration process for new projects. This standardization achieved a truly portable and reusable verification environment that maintains consistency while adapting to diverse product requirements. It also allowed early bug discovery and streamlined the verification process.
The impact of Aparna’s leadership extended far beyond immediate project success. The framework notably improved verification processes across multiple product lines, dramatically reducing the time required to establish robust verification environments for new designs. Perhaps most significantly, the framework significantly lowered the barrier to entry for engineers new to specific projects, enabling them to quickly become productive in verification activities without extensive ramp-up periods. It also reduced the overall verification timeline.
Stakeholder reception to the framework was overwhelmingly positive, with verification teams across the organization adopting the methodology for end-to-end performance verification. The framework’s success was formally recognized at the prestigious Cirrus Logic Innovation Conference 2017, where Aparna Mohan presented a poster highlighting the methodology’s benefits and implementation details.
For Aparna Mohan personally, the project represented a significant career milestone, showcasing her technical leadership and methodology development skills. The achievement directly contributed to her promotion to Senior Design Verification Engineer – a testament to the framework’s organizational impact and her exceptional contributions to verification excellence.
Further cementing her position as a verification thought leader, Aparna serves on the technical program committee of the prestigious DVCON 2025 Europe conference, where she helps shape industry discussions on verification methodologies and emerging technologies. Her expertise and judgment have also been recognized through her appointment as an industry expert judge for the Globee awards, evaluating excellence in technology innovation.
As an SCRS fellow, Aparna continues to contribute to scholarly research and practical applications in chip verification methodologies. Beyond her technical contributions, she serves as a mentor at “Rewriting the Code,” where she provides guidance, career advice, and industry insights to college students and early-career women in technology, helping to foster the next generation of diverse technical talent.
As a published researcher with papers in international conferences and a regular presenter of innovative verification methodologies at industry events, Aparna Mohan continues to advance the field while solving complex verification challenges.
About Aparna Mohan
Aparna Mohan is a distinguished Design Verification Engineer with over 11 years of expertise in pre-silicon verification and methodology implementation. Her technical portfolio includes contributions to 14 successfully taped-out ASIC products across various applications. Aparna Mohan specializes in functional verification methodologies (UVM, System Verilog), SVA, and formal verification techniques, establishing her as a recognized expert in comprehensive verification approaches.
She holds a Master’s degree from North Carolina State University and a Bachelor’s degree from the University of Kerala, providing a robust foundation for her technical achievements. Before her semiconductor career, Aparna worked at the Indian Space Research Organization, where she contributed to satellite technology development and the Indian Mars mission.
Her commitment to advancing the field is evident through her published research papers in international conferences and regular presentations on innovative verification methodologies at industry events. Aparna Mohan continues to push the boundaries of verification excellence while mentoring the next generation of verification engineers.
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