Intel’s “18A” chip-manufacturing process, which promises to turn around the company’s business, is ready to start accepting customer orders.
The company published a new website hailing the arrival of 18A, which is scheduled to start “tape outs” in the first half of the year, meaning the chip process has entered the final design process. Intel then expects to kick off volume production in the second half of 2025, including for its “Panther Lake” laptop chip and the “Clearwater Forest” server processors.
18A is especially important because it’s designed to be competitive with the leading-edge chip-manufacturing process from Taiwan’s TSMC, which counts Apple, AMD, and Nvidia as clients. “I’ve bet the whole company on 18A,” former Intel CEO Pat Gelsinger said last year before abruptly retiring.
(Credit: Intel Foundry)
Intel’s website also points out that 18A represents “the earliest available sub-2nm advanced node manufactured in North America, offering a resilient supply alternative for customers.” This comes as President Trump plans on tariffing foreign-made chips, including those from TSMC, in an effort to push tech companies to migrate their electronics manufacturing to the US.
Trump has warned his tariffs will start at “25% and higher” for foreign-made chips. That’s a problem for TSMC and its clients since most of the company’s manufacturing happens in Taiwan, although its first fab in Arizona recently started chip production.
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On the flip side, the tariffs could be a boon for Intel, which began making a new push into the foundry business starting in 2021. The company has since struck deals to build chips for Arm, Amazon AWS, and Microsoft using the 18A process, which has been developed at Intel facilities in Arizona and Oregon.
The big question is whether the 18A chips will meet the hype. So far, Intel has only said the manufacturing process features an “up to 15% better performance per watt and 30% better chip density” versus the company’s older Intel 3 process node. The resulting chips will also contain a “PowerVia” and “RibbonFET” architecture to cut down on interconnect bottlenecks while improving the power efficiency.
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About Michael Kan
Senior Reporter
